Methods of manufacturing copper interconnect systems

ABSTRACT

An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier. The allow seed layer may also be over the dielectric etch stop and diffusion barrier layer, and the alloy seed layer may be in contact with the first conductive region.

CROSS-REFERENCE

This application is a continuation of U.S. patent application Ser. No. 12/554,137, filed Sep. 4, 2009, currently pending, which is a continuation of U.S. patent application Ser. No. 12/056,163, filed Mar. 26, 2008, now U.S. Pat. No. 7,585,766, which is a continuation of U.S. patent application Ser. No. 11/278,914, filed Apr. 26, 2006, now U.S. Pat. No. 7,372,152, which is a continuation of U.S. patent application Ser. No. 10/803,475, filed Mar. 18, 2004, now U.S. Pat. No. 7,026,714, which claims the benefit of U.S. Provisional Application No. 60/455,496, filed Mar. 18, 2003, the entireties of all of which are incorporated herein by reference.

TECHNICAL FIELD

The present invention relates to the field of electronics, and, more particularly, to semiconductor devices including copper interconnects and related methods. Even more particularly, the invention relates to reliability improvements for copper interconnects.

BACKGROUND

Doped seed layers have been disclosed in the prior art, their presence directed to various objectives. These include U.S. Pat. Nos. 5,969,422 to Ting et al.; 6,249,055 to Dubin; 6,181,012 to Edelstein et al.; 6,066,892 to Ding et al.; and 6,462,675 to Paranjpe et al. But none of these inventions discloses a copper interconnect system where a copper via to underlying copper interconnect makes a substantially direct copper to copper connection without the presence of an intervening diffusion barrier. The presence of such a barrier tends to degrade the electromigration resistance of the system.

Two prior art patents disclose where direct or near direct copper-to-copper interfaces are formed at the base of a copper via to an underlying copper interconnect. U.S. Pat. No. 6,169,024 to Hussein forms a seed layer of varying thicknesses against a refractory metal diffusion barrier as are common in the industry, and then etches both refractory metal barrier and the dielectric cap material at the base of the via with the seed material acting as a mask. Such a process is inherently extremely difficult to control, the main problem residing in controlling the required wide variation in seed layer thicknesses.

U.S. Pat. No. 6,380,075 to Cabral, Jr. et al. discloses a process which purports a CVD method wherein the liner thickness is very thin or nonexistent at the base of the via and yet of sufficient thickness on the horizontal surfaces under the copper interconnect regions. Such a process is also inherently extremely difficult to control. Neither of these prior art references discloses use of a metal-based cap layer, alloy seed layers, or methods of improved interface bonding.

U.S. Patent Application Publication No. 2002/0106895 A1 to Chung discloses a method to provide direct copper-to-copper contact at the base of a copper dual-damascene via. But no seed layer is disclosed, and no methods for improving the adhesion at the various copper interfaces are disclosed. Upon application of high current density, any copper interface where weak bonding of the adjoined film or material is present, tends to degrade the electromigration and stress induced migration failure rates.

U.S. Patent Application Publication No. 2003/0190829 A1 to Brennan also proposes a method to provide direct copper-to-copper contact at the base of a copper dual-damascene via. But no capping or seed layers are disclosed, and no methods for improving the adhesion of the various interfaces are disclosed. The method requires use of high dielectric constant nitride-based etch stop and diffusion barriers. This tends to degrade RC delays in the copper interconnects. A more serious concern is that the patent discloses no diffusion barriers for the edges of the copper interconnects.

SUMMARY

In view of the foregoing background, it is therefore an object of the present invention to provide a copper interconnect system which uses a conductive, metal-based cap layer, and substantially direct copper-to-copper contact at the interface of the copper via to the underlying copper interconnect. The invention, with its several embodiments, is focused on damascene type implementations. Within the dual-damascene structure, doped, that is, alloy seed layers may be used both against dielectric (insulating) and metal-based or conductive diffusion barriers. The resulting structure has improved resistance against electromigration (EM) and stress induced migration failures.

The invention provides enhanced adhesion or interfacial bonding for all critical interfaces including: seed layer to dielectric diffusion barrier layer; cap layer to main copper region; conductive trench liner barrier materials to seed layer; and conductive trench liner barrier materials to main surrounding inter-level dielectric (ILD). Use of high dielectric insulators may be minimized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-3 are schematic cross-sectional views of an integrated circuit during manufacturing thereof in accordance with a first embodiment of the present invention.

FIGS. 4-6 are schematic cross-sectional views of an integrated circuit during manufacturing thereof in accordance with a second embodiment of the present invention.

FIGS. 7 and 8 are schematic cross-sectional views of alternate embodiments of the invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The present invention now will be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

The following first embodiment is directed to improving the various weaknesses of prior art copper interconnect technology as discussed in detail above. These include weak bonding of the copper interconnect at the various interfaces present. Among various improvements, this invention teaches the use of certain metals and alloys to improve the bonding. This results in greatly reduced interface diffusion rates. This improves EM resistance, and reduces stress induced migration failure rates.

Referring to FIG. 1, a first Damascene-type interconnect comprising copper 3 is formed in an SiO₂ or low-k type insulator 1 that, in turn, is on or adjacent a substrate 30. A liner 4 is formed by PVD, CVD or by (atomic layer deposition) ALD or by other methods, of Ta, Ta/TaN, Ta/TaN/Ta or other combinations thereof, or, for adhesion enhancement, an alloy or mixture comprising Ti added to Ta, Cr, Mo, W, Rh, Ru or R—such alloys yielding improved adhesion to copper based metal 3. The barriers may also contain nitrogen or Si. In general, nitrogen tends to reduce grain boundary diffusion rates, and small concentrations of Si tend to produce amorphous or more amorphous films. The liner 4 may have a thickness in the range of one monolayer to 200 Å. The added Ti concentration would range from 1 to 30%. Diffusion barrier liners of rhodium, ruthenium or rhenium may also be used as disclosed in U.S. Pat. No. 6,441,492, the entire contents of which are incorporated herein by reference.

Following the planarization step using CMP, as indicated by a plane shown by the dashed line 21, a selective metal-based cap 5 is then added to the surface of interconnect 3 as described above. The cap 5 may be formed using electroless Co-based alloys, such as Co—W—P or Co—W—B, or may be the Ru system described above, or another selectively deposited conductive system offering both a measure of good or improved adhesion to copper and an adequate diffusion barrier against penetration of copper into the surrounding interlevel dielectric ILD. (An alternative embodiment for a Ru-based barrier is described below.)

Dielectric layer 2 is then formed over the capped interconnect. Dielectrics used for the ILD may be SiO₂-based or may be one of various low-k insulators as known in the art. These include films such as: oxides containing fluoride (FSG), SiLK™, Black Diamond™, various spin-on organics, HSQ, various high-porosity SiO₂-based types, and many others now under investigation and refinement in the industry.

Etch stop and dielectric diffusion barriers 6 are then formed using silicon nitride, Si—C, Si—C—N'O, Si—O—N, or Si—C—N materials as are known in the art. Dielectric layer 7 and etch stop and optional diffusion barrier layer 8 are added prior to the formation of opening 9. Opening 9 is then formed using photoresist layers, not shown, as is known for the via for the first dual-damascene process. Differential etch rates for the dielectric diffusion barriers are not required in this process, so the materials may be selected for a minimum dielectric constant. The Co-based barrier system 5 is then removed over the copper 3 using argon bombardment or backsputter cleaning For a Ru-based embodiment, the Ru metal may be removed in fluorine-based RIE plasma chemistry. For a Ru-based cap an alternative is to remove the cap material upon etching the trench for the interconnect, that is, etch the film after the via first step. Photoresist is then added and a trench for interconnect 12 is formed by plasma etching as is known in the art. Fluorine or chlorine plasma chemistries do not appreciably attack exposed copper-based metal 3.

FIG. 1 shows the system at the intermediate step following opening of the trenches for a second overlying interconnect 12. FIG. 2 shows the structure following the deposition and anisotropic etchback of a conductive diffusion barrier 8 which can be of similar composition to layer 4. Alternately, the barrier may be a dielectric barrier such as silicon nitride, Si—C—N—O or Si—C—N. A diffusion barrier is deposited and is anisotropically etched back leaving edge protection layers 10 (FIG. 2). Materials, such as those used for layer 8 could be used. Selective plasma etching chemistries may be employed using chlorine or fluorine or combinations thereof as are known in the art. The copper material 3 is exposed at the base of the via. The exposed copper at this point may be cleaned and optionally passivated using displacement plating with a metal more noble than copper, such as Ag, Pd or Pt. This film thickness may be one monolayer up to about 50 Å. Following this optional plating, the surrounding dielectrics nay be cleaned with chemical complexing agents. The exposed copper 3 may also be sputter cleaned prior to the formation of layer 11. The passivation step provides substantially no, or only partial, diffusion barrier properties at this copper 3 to copper 12 interface.

FIG. 3 shows the structure after deposition of an alloy seed layer 11. This alloy comprises copper and Ta, Cr, Mo, or W forming a mixture or alloy with improved adhesion to dielectric diffusion layer 6. The dopants Ta and Cr are preferred. The alloy seed layer 11 may be deposited by PVD, or other methods such as CVD, such that a reasonably conformal film is created. The added refractory metals may be in atomic concentrations ranging from 1 to 30% or more. Seed layer 11 is designed to be strongly copper-like and does not contain sufficient dopant or alloying material such that it behaves as a diffusion barrier. Copper metal or copper alloy 12 may be then formed by electroplating or by electroless plating as is known in the art. A cap 13 is added to the copper or copper alloy layer 12 in like manner to layer 5. The copper or copper-based metal 12 makes direct, or near direct contact, or equivalent direct contact, or contact without the intervening presence of a substantial or diffusion-blocking thickness of an immiscible or passive diffusion barrier, to copper or copper alloy metal 3. This main region copper 12 to lower level copper 3 contact is made through seed layer 11 comprising copper.

Referring now additionally to FIGS. 4-6, a second embodiment provides a conductive coating or cap layer on the copper interconnect surface for the purpose of interface diffusion rate reduction. The coating is not a robust diffusion barrier, and for that reason it is covered by a dielectric diffusion barrier. The coating is etchable in halide-containing anisotropic plasma etching chemistries (RIE), and may be removed so that overlying copper vias may make a more direct copper-to-copper connection. This aids the prevention of copper flux divergence at the base of a via, a phenomenon which tends to reduce EM resistance. This embodiment also has no substantial diffusion barrier thickness remaining at the base of copper vias.

Following FIG. 4, a copper based interconnect 12 is formed over substrate 11 by a damascene-type process. The trench is lined with diffusion barrier 13 as described in the first embodiment above. The film 23 below the dashed line 22 is an insulating layer as is known in the art, and is described in the first embodiment above. After CMP, terminating approximately along the dashed line 22 shown, the exposed copper interconnect 12 is passivated using palladium or platinum. The Pt or Pd films 14 may be selectively applied by immersion plating or by electroless plating. A film ranging in thickness from one monolayer to about 200 Å may be applied. Following the application of this metal film, the device may be annealed at 300-500° C. to interdiffuse the plated metal and copper. Both metals form continuous solid solutions with copper, and upon annealing, form a hardened surface alloy layer which retards the surface transport of copper upon elevated temperature or EM stress. Both metals are plasma etchable in halide chemistries. Alternately, the heat treatment could be performed later in the process.

Following the surface passivation step insulating films 15, 16, 17, 18, and 19 are deposited as is known in the art. Films 16 and 17 are SiO₂-based or may be one of various low-k insulators as known in the art. These include films listed in the first embodiment. Films 15, 18 and 19 are etch stop diffusion barrier layers, such as silicon nitride or Si—C or PECVD Si—C—N or Si—C—N—O and other “carbide” type films as are known in the art.

As shown in FIG. 4, the stack of insulating films is plasma etched, employing a photoresist layer, not shown, down to etch stop 15, as is known in the art. After applying another PR layer, not shown, which defines the trench region for a second copper based interconnect, not shown completed, the trench region 32 is etched, and film 15 and unreacted or non-interdiffused portions of passivation film 14 are removed down to the surface of material 12 comprising copper. This may be seen in FIG. 5.

Following this step, a diffusion barrier 33 is formed as described in the first embodiment in the form of an edge spacer.

An alternative embodiment is etching this barrier film, which results in edge film 33, to a non-zero thickness of 20 Å or less such that it is a partial barrier in the horizontal regions. In this case, the barrier film is electrically conducting.

Following this step, an alloy seed layer 34 is formed as described in the first embodiment. FIG. 6 shows the device following the formation of alloy seed layer 34.

It may be noted that the preferred alloying elements Ta and Cr for the alloy seed layer are carefully selected. They require two properties to perform optimally in this invention:

(1) They should be capable of forming strong M—O bonds so that good adhesion is available against the dielectric barriers such as layer 18. The Gibbs function free energy per oxygen bond for metals decreases as: Ti>Al>Ta≈Cr>Si>Mo≈W≈Co≈Re>Cu>Ru. The preferred metals also form strong M—N bonds.

(2) They should be immiscible (passive) with copper so that negligible interdiffusion occurs from the alloying elements into the main or thicker copper interconnect region formed above and onto film 34.

The main current-carrying copper region above film 34 may be unalloyed or lightly alloyed with elements which only cause small increases in resistivity such as, for example, Ag or Cd. Interdiffusion of substantial concentrations of Ta, Cr, Mo or W would cause significant increases in the resistivity in the main current-carrying copper material formed onto the alloy seed layers. If this were to happen, the system may not be viable. An exemplary alloy is Ta and copper, with the Ta concentration approximately 5 to 30 at %. A preferred alloy may be 10 to 20 at % Ta in copper. A preferred method of deposition of the seed alloy is PVD or IPVD (ionized PVD) as developed by Applied Materials and others. The sputtering parameters may be adjusted to maximize edge coverage over bottom coverage. The films may also be applied by CVD.

Finally, the bulk of the copper based interconnected is formed onto the seed layer and planarized using CMP as described in the first embodiment. The bulk copper is typically electroplated.

An alternate embodiment for the metal cap layer over copper is now disclosed. This barrier, in its more robust form, should both firmly bond to both copper and the overlying oxide insulation or dielectric, and offer passive diffusion barrier characteristics as well. An exemplary system is the following material stack: plated copper/displacement plated silver followed by displacement palladium/selective electroless plated Ru/light oxidation. This system requires no overlying dielectric diffusion barrier; thus the ILD dielectric constant is minimized.

FIGS. 7 and 8 show the expected metallurgy of the system upon annealing. A copper interconnect surface such as that of copper region 3 prior to application of film 5 is represented in FIG. 7 as electroplated copper 35. Approximately 20 Å of immersion silver 36, approximately 10 Å of immersion palladium 37, and approximately 100 Å of electroless Ru 38 are applied over copper layer 35. Upon annealing, at about 400° C. in a mixture of N₂ and O₂, solid state diffusion and oxidation of the Ru occurs producing the structure of FIG. 8 represented by Cu phase 41, Cu+Pd solid solution 42, Ag+Pd solid solution 39, 1-2% Ru in Pd₂ phase 43, and conductive RuO₂ surface layer 40. Grain boundaries 44 would contain some oxidized Ru in the remaining Ru layer derived from Ru 38.

Upon application of an overlying dielectric such as film 2, the system provides a firm and strongly bound transition from copper to diffusion barrier to overlying dielectric.

Using non-cyanide complexing agents, various solutions may be prepared for immersion plating bright films of silver to copper. Silver added to copper has the smallest known effect on resistivity of all the elements. Since reduction potentials increase as Cu>Ru>Rh>Ag>Pd>Pt>Au, Pd may be immersion plated over Ag. Such an action also fills any pinholes in the Ag layer making the final film more dense.

Solutions for immersion plating of palladium are known. Ru may be electroless plated using hydrazine as a reducing agent. The final film stack may be annealed in N₂ followed by N₂/O₂ forming a conductive RuO₂ layer and simultaneously stuffing the grain boundaries of the Ru passive barrier.

For the embodiments where the Ru and RuO₂ layer were at the base of a via, the films could be removed or thinned. Since Ru forms volatile fluorides, this can be accomplished during the anisotropic plasma etching through the via ILD. This provides a more direct Cu to Cu connection from via to interconnect.

In recent years, Ru based barriers have been under investigation as diffusion and oxidation barriers for very high-k, stacked, DRAM capacitor applications.

Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the invention is not to be limited to the specific embodiments disclosed, and that other modifications and embodiments are intended to be included within the scope of the appended claims. 

1. An integrated circuit comprising: a substrate; a first dielectric layer disposed over the substrate; a trench formed within the first dielectric layer; a metal-based first liner disposed within the trench; a first conductive region formed within the trench and over, at least in part, the first liner; a metal-based cap layer disposed over the first conductive region; an etch stop layer disposed over the cap layer and in direct contact with the first dielectric layer; a second dielectric disposed over and in direct contact with the etch stop layer; a via opening passing through the second dielectric layer and the cap layer; a metal-based second liner disposed on the sidewalls of the via opening; and a second conductive region formed within the via opening, wherein the second conductive region is in electrical contact with the first conductive region.
 2. The integrated circuit of claim 1, further comprising: an alloy seed layer disposed on the sidewalls and bottom of the via opening between the second liner and the second conductive region.
 3. The integrated circuit of claim 2, wherein the alloy seed layer comprises Cu.
 4. The integrated circuit of claim 1, wherein the first conductive region comprises Cu.
 5. The integrated circuit of claim 1, wherein the metal-based cap layer comprises a Co-based alloy.
 6. The integrated circuit of claim 5, wherein the Co-based alloy comprises at least one of Co—W—P or Co—W—B.
 7. The integrated circuit of claim 5, wherein the Co-based alloy comprises an electroless Co-based alloy.
 8. The integrated circuit of claim 1, wherein the metal-based cap layer comprises at least one of Co, B, W, P, or Ru.
 9. The integrated circuit of claim 1, wherein the metal-based cap layer is a selectively-deposited cap layer.
 10. The integrated circuit of claim 1, wherein the second conductive region comprises Cu.
 11. The integrated circuit of claim 1, wherein the etch stop layer comprises at least one of the following materials: silicon nitride, Si—C, Si—C—N—O, Si—O—N, or Si—C—N.
 12. The integrated circuit of claim 1, wherein the first liner comprises at least one of the following materials: Ta, Ta/TaN, Ta/TaN/Ta, or other combinations thereof.
 13. The integrated circuit of claim 1, wherein the first liner comprises an alloy or mixture including Ti added to Ta, Cr, Mo, W, Rh, Ru or Re.
 14. The integrated circuit of claim 1, wherein the second liner comprises at least one of the following materials: Ta, Ta/TaN, Ta/TaN/Ta or other combinations thereof.
 15. The integrated circuit of claim 1, wherein the second liner comprises an alloy or mixture including Ti added to Ta, Cr, Mo, W, Rh, Ru or Re. 